1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly to semiconductor memories including memory cells, each using adjacent two diffusion wires as drain and source, respectively, and a word line as gate.
2. Description of Related Art
The semiconductor memories of the above kind have been widely used as large-capacity memories. The semiconductor memories have accomplished high-speed operation due to a memory cell array made of blocks separated every M word lines in column direction. The blocks share N+1 virtual ground wires, and N main bit lines, each between the adjacent two of the virtual ground wires. Diffusion wires are provided. The diffusion wires are distant one fourth (¼) as much as the virtual ground wires are. The adjacent two blocks in column direction are symmetric with respect to an imaginary line separating them. Memory cells in each column share the adjacent two diffusion wires as drains and sources, and they use the M word lines as gates, respectively. Thus, the blocks have memory cells in M rows and 4N columns. Referring to the accompanying drawings, FIG. 8 is a fragmentary circuit diagram showing a portion of a memory cell array of the semiconductor memory of this kind. U.S. Pat. No. 5,392,233, Iwase, Feb. 21, 1995 (=JP-A 5-167042) shows a ROM using a circuit diagram of this kind.
FIG. 8 shows 3 (three) blocks separated every 3 (three) word lines in column direction. The separated blocks, namely, block 0, block 1 and block 2, share 2 (two) virtual ground wires D3 and D5, and 2 (two) main bit lines D4 and D6, each between the adjacent two of the virtual ground wires. The adjacent two blocks in column direction are symmetric with respect to an imaginary line separating them. Ground-connection to the virtual ground wires is selectively made in response to address operation. The main bit lines are selectively addressed and sensed. In FIG. 8, for illustrative purpose only, the blocks are three in number, the word lines in each block are three in number, the virtual ground wires are two in number, and the main bit lines are two in number.
Diffusion wires are provided. The diffusion wires are distant one fourth (¼) as much as the virtual ground wires are. In each block, memory cells in each column share the adjacent two diffusion wires as drains and sources, and they use three word lines as gates, respectively. In each block, between the adjacent two of the dummy wires, for example, D3 and D5, memory cells in 3 (three) rows and in 4 (four) columns are grouped as a memory cell unit, namely, a four-column memory cell unit. Each block includes four column select lines, two on one ends of the diffusion wires, the other two on the other ends. Further, it includes three bit column select transistors and three ground column select transistors per each four-column memory cell unit.
In the block 1, for example, on one end side of diffusion wires BN11 to BN17, three bit column select transistors S41, S40 and S42 are connected to the main bit line D4. The bit column select transistor S41 has diffusion layer connected to the main bit line D4. It uses the middle diffusion wire BN13 for one four-column memory cell unit as drain or source and the column select line BS11 as gate. Each of the bit column select transistors S40 and S42 has diffusion layer connected to the main bit line D4. The bit column select transistor S40 uses the diffusion wire BN12, lying on one side of and next to the middle diffusion wire BN13, as drain or source and the column select line BS10 as gate. The bit column select transistor S42 uses the diffusion wire BN14, lying on the opposite side of and next to the middle diffusion wire BN13, as drain or source and the column select line BS10 as gate.
In the block 1, on the other end side of the diffusion wires BN11 to BN17, another three ground column select transistors S51, S50 and S52 are connected to the virtual ground wire D5. The ground column select transistor S51 has diffusion layer connected to the virtual ground wire D5. It uses the boundary diffusion wire BN15 for one four-column memory cell unit as drain or source and the column select line BS10 as gate. Each of the ground column select transistors S50 and S52 has diffusion layer connected to the virtual ground wire D5. The ground column select transistor S50 uses the diffusion wire BN14, lying on one side of and next to the boundary diffusion wire BN15, as drain or source and the column select line BS11 as gate. The ground column select transistor S52 uses the diffusion wire BN16, lying on the opposite side of and next to the boundary diffusion wire BN15, as drain or source and the column select line BS11 as gate.
Next, it is now explained how this conventional semiconductor memory selects a memory cell. As is readily understood from the preceding description, the memory cell array of each block is identical in structure every four-column memory cell unit. In each block, the memory performs the same or symmetrical select action every four-column memory cell unit. Thus, description on action to select each of four memory cells M1, M2, M3 and M4 appears to be sufficient. In the block 1, the four memory cells M1 to M4, lying between the virtual ground wires D3 and D5, are connected to the word line W11.
During select operation of these memory cells M1 to M4, the word line W11 of the block 1 only has high level so that the memory cells connected to this word line W11 have ON or OFF level selectively depending on the data to be memorized. The other word lines W10, W12, W00 to W02, and W20 to W22 have low levels so that all of the memory cells connected to them have OFF levels.
In the case where the memory cell M1 is selected, in response to address operation, ground-connection to the virtual ground wire D3 and precharge to the virtual ground wire D5 are selectively made, connection of the main bit line D4 to a sense amplifier is selectively made to be sensed, and the column select line BS10 has high level. Then, the ground column select transistors S31 and S51 have ON levels, respectively, and the bit column select transistors S40 and S42 have ON levels, respectively, making ground-connection to and sensing-connection to the diffusion wires BN11 and BN12, respectively, which are on both sides of a memory cell column including the memory cell M1. Under this condition, ON or OFF status of the memory cell M1 connected to the word line W11 determines sense current flowing through the main bit line D4, which is detected by the sense amplifier.
In the case where the memory cell M2 is selected, in response to address operation, ground-connection to the virtual ground wire D3 and precharge to the virtual ground wire D5 are selectively made, connection of the main bit line D4 to the sense amplifier is selectively made to be sensed, and the column select line BS11 has high level. Then, the ground column select transistors S32 and S50 have ON levels, respectively, and the bit column select transistor S41 has ON level, making ground-connection to and sensing-connection to the diffusion wires SN12 and BN13, respectively, which are on both sides of a memory cell column including the memory cell M2. Under this condition, ON or OFF status of the memory cell M2 connected to the word line W11 determines sense current flowing through the main bit line D4, which is detected by the sense amplifier.
In the case where the memory cell M3 is selected, in response to address operation, ground-connection to the virtual ground wire D5 and precharge to the virtual ground wire D3 are selectively made, connection of the main bit line D4 to the sense amplifier is selectively made to be sensed, and the column select line BS11 has high level. Then, the ground column select transistors S50 and S32 have ON levels, respectively, and the bit column select transistor S41 has ON level, making ground-connection to and sensing-connection to the diffusion wires BN14 and BN13, respectively, which are on both sides of a memory cell column including the memory cell M3. Under this condition, ON or OFF status of the memory cell M3 connected to the word line W11 determines sense current flowing through the main bit line D4, which is detected by the sense amplifier.
In the case where the memory cell M4 is selected, in response to address operation, ground-connection to the virtual ground wire D5 and precharge to the virtual ground wire D3 are selectively made, connection of the main bit line D4 to the sense amplifier is selectively made to be sensed, and the column select line BS10 has high level. Then, the ground column select transistors S51 and S31 have ON levels, respectively, and the bit column select transistors S42 and S40 have ON levels, respectively, making ground-connection to and sensing-connection to the diffusion wires BN15 and BN14, respectively, which are on both sides of a memory cell column including the memory cell M4. Under this condition, ON or OFF status of the memory cell M4 connected to the word line W11 determines sense current flowing through the main bit line D4, which is detected by the sense amplifier.
As is readily seen from the preceding description, precharge is always made to one of the virtual ground wires D3 and D5 of the four-column memory cell unit, preventing the four-column memory cell unit and the adjacent cell units from sharing charge via the selected memory cell, ensuring individual unit operations to select its memory cells, M1 to M4, for example.
FIG. 9 is a fragmentary view of the illustrated portion of layout of the previously described conventional semiconductor memory, illustrating a portion of the block 1 shown in FIG. 8. As is readily seen from FIG. 9, the conventional semiconductor memory has accomplished a considerable increase in storage capacity because each block has memory cells using the adjacent one of equidistant diffusion wires as drain or source and one of word lines as gate, and each block has a connector per each four-column memory cell unit for alternative connection to one of main bit lines and the adjacent diffusion wire. Besides, the conventional semiconductor memory has accomplished high speed operation because the amount of load applied to the main bit lines has dropped by employing a memory cell array composed of blocks separated in column direction at every plural number of word lines to reduce memory cells, in number, selectively connected in parallel to the main bit lines.
The conventional semiconductor memory is capable of accomplishing a further high speed operation with high-speed sense amplifiers due to a sufficiently large margin allowed by small variations in shunt resistance of current flow paths from the main bit lines to the adjacent ones of the virtual ground wires with different memory cells to be selected. Specifically, in the conventional semiconductor memory, the current flow path is composed of equal bit column select transistors, equal memory cells, equal ground-column select transistors, and a single diffusion line and the shunt resistance almost remains unaltered irrespective of which different memory cells is selected.
For further understanding of the above-mentioned issue, reference is made to Iwase, U.S. Pat. No. 5,392,233, particularly to description of FIGS. 5 and 6 ranging from column 6 line 59 to column 7 line 56, which United States Patent as been incorporated herein by reference.
With continuing reference to FIG. 8, according to the conventional semiconductor memory, in order to select, for example, the memory cell M1 or M4, the bit column select transistors S40 and S42 have ON levels, respectively, in response to address operation, allowing charge to the diffusion wires BN12 and N14 from the main bit line D4, and allowing charge to the diffusion wire BN13 depending on the status of the memory cell M2 or M3. In order to select, for example, the memory cell M2 or M3, the bit column select transistor S41 has ON level in response to address operation, allowing charge to the diffusion wire BN13 from the main bit line D4, and allowing charge to the diffusion wire BN14 or BN12 depending on the status of the memory cell M3 or M2.
In the conventional semiconductor memory, as the number of diffusion wires to be charged from the main bit line ranges from one to three depending on address selection and status of memory cells, the amount of charge load capacity to be charged from the main bit line D4 varies three times, narrowing margin, causing a considerable delay in sense judgment time required for a sense amplifier to sense, via the main bit line, appearance of current. This poses a problem that further high-speed operation is difficult to accomplish.
FIGS. 10(A), 10(B) and 10(C) are graphical representations illustrating varying of delay in sense judgment time with different levels in charge load capacity. FIG. 10(A) shows variations of ON level voltage and OFF level voltage appearing for ON level and OFF level of a selected memory cell, respectively, when the load capacity for charge is mean and normal. FIG. 10(B) shows variation of ON level voltage and OFF level voltage appearing for ON level and OFF level of a selected memory cell, respectively, when the load capacity for charge is greater than the mean. FIG. 10(C) shows variation of ON level voltage and OFF level voltage for ON level and OFF level of a selected memory cell when the load capacity is less than the mean. With reference to FIG. 10(A), commonly, accounting for the mean load capacity for charge and margin determines a reference level used by the sense amplifier in making judgment. Address select operation and status of a memory cell selected may cause load capacity for charge to become greater than the mean. In this case, as the charge capacity is constant, undercharge takes place, lowering both ON level and OFF level voltages as shown in FIG. 10(B). Under this condition, margin becomes narrow and a considerable delay in judgment time required for sensing OFF level voltage is observed. If load capacity for charge becomes less than the mean, as the charge capacity is constant, overcharge takes place, elevating both ON level and OFF level voltages as shown in FIG. 10(C). Under this condition, margin becomes narrow and a considerable delay in judgment required for sensing ON level voltage is observed.
As described before, the memory cell array of the conventional semiconductor memory is made of blocks separated every plural word lines in column direction. The conventional semiconductor memory needs one region on one ends of the diffusion wires for two column select lines and three bit column select transistors per every four-column memory cell unit and another region on the other ends of the diffusion wires For two column select lines and three ground column select transistors per the four-column memory cell unit. The proportion of an area occupied by these regions to the overall area of a chip grows bigger and bigger as the number of blocks increases. For a further high speed operation, one measure would be increasing the number of blocks to reduce the number of memory cells connected in parallel to each main bit line for a reduction in load applied to the main bit line. This measure, however, poses a problem that the overall area of a chip inevitably increases.
In order to restrain the overall area of the chip from increasing, the incorporated U.S. Pat. No. 5,392,233 proposes arranging on one ends of diffusion wires one column select line and on the other end of the diffusion wires another column select line. According to this proposed layout, the path of current flowing from a main bit line to the associated virtual ground wire involves a U turn at a memory cell selected by a word line. Thus, the path has varying of values in shunt resistance with difference word lines used in selecting memory cells. Sufficient margin cannot be guaranteed, making it difficult to use sense amplifiers designed for high speed operation, failing to accomplish a satisfactory level of high-speed operation.
Accordingly, the present invention aims at accomplishing a further speed-up in operation of semiconductor memories without any substantial increase in the overall area of a chip.